1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same and, more specifically, it relates to a semiconductor memory device suitable for a 1 transistor-1 capacitor type dynamic RAM and a method for manufacturing the same.
Co-pending applications related to the present invention are U.S. Ser. No. 904,843, U.S. Ser. No. 075,083 and U.S. Ser. No. 104,921.
2. Description of the Prior Art
As the dynamic RAM has become smaller and smaller, the capacitor regions become smaller and the amount of charges stored therein also becomes smaller. As a result, it becomes a serious problem that the reliability is lowered due to soft errors or the like. Various improvements are proposed to increase the storage capacitance. One of these improvements is a trench capacitor cell, in which a trench is formed in the semiconductor substrate. Related prior arts are Japanese Patent Laying-Open Gazette No. 67862/1987, M. WADA et al. "A folded Capacitor Cell (F.C.C.) for Future Megabit DRAMs", IEDM, Tech. Dig. pp. 244-247, (1984), K. Nakamura et al. "Buried Isolation Capacitor Cell (BIC) for Megabit MOS Dynamic RAM", IEDM, Tech. Dig. pp. 236-239, (1984), W. F. Richardson et al., "A Trench Transistor Cross-Point DRAM Cell", IEDM, Tech. Dig. p. 714 (1985). In addition, Japanese Patent Laying-Open Gazette No. 104466/1988 and Japanese Patent Laying-Open Gazette No. 124455/1988 are also related to the present invention, although they became known after the priority date of the present application.
FIG. 4 shows an example of the prior art which is called an isolation-combination type trench capacitor cell.
Referring to FIG. 4, a plurality of blocks 1 (only one is shown) are formed on a main surface of the semiconductor substrate, each formed to be approximately rectangular solid, four sides thereof surrounded by trenches 2 formed lengthwise and breadthwise. A pair of switching transistor regions 4 (only one is shown) is arranged on the block 1 on the side of the main surface 3 of the semiconductor substrate. A pair of capacitor regions 5 (only one is shown) is arranged on a pair of side wall surfaces of the block 1 which are parallel to each other.
A gate oxide film 6a and a gate electrode 6b thereon are formed on that portion of the main surface 3 which is near the said capacitor region 5 in the said switching transistor region 4. A pair of source/drain regions 7 and 8 is formed on the side of the main surface 3 of the block 1 sandwiching the gate oxide film 6a and the gate electrode 6b.
In the said capacitor region 5, a capacitor electrode layer 9 is formed on the side wall surface of the block 1. The upper end portion of the capacitor electrode layer 9 is connected to one source/drain region 8. Although omitted in FIG. 4, an insulating layer and a second electrode layer are arranged in the trench 2, forming, together with the electrode layer 9, the capacitor region 5.
Although not shown, a bit line is connected to the source/drain region 7 and a word line is connected to the gate electrode 6b. The said switching transistor region 4 and the capacitor region 5 form one memory cell of a 1 transistor-1 capacitor type dynamic RAM.
In the above mentioned conventional semiconductor memory device, the transistor region 4 and the capacitor region 5 should be isolated from each other. Therefore, the capacitor region 5 can be formed only on two sides out of four sides of each block 1. For this reason, in the said conventional semiconductor memory device, the capacitor area could not be made large enough to ensure a large amount of charge to be stored.